1. Field
Various embodiments of the present invention relate to a technology for recording information used for operating a semiconductor device.
2. Description of the Related Art
FIG. 1 is a block view illustrating a repair operation of a typical memory device.
Referring to FIG. 1, the memory device includes a cell array 110, a row circuit 120, and a column circuit 130. The cell array 110 includes a plurality of memory cells. The row circuit 120 activates a word line selected based on a row address R_ADD. The column circuit 130 accesses (reads or writes) the data of a bit line selected based on a column address C_ADD.
A row fuse circuit 140 stores a row address corresponding to a failed memory cell of the cell array 110 as a repair row address REPAIR_R_ADD. A row comparison circuit 150 compares the repair row address REPAIR_R_ADD stored in the row fuse circuit 140 with the row address R_ADD inputted from the exterior (an external source) of the memory device. When the repair row address REPAIR_R_ADD coincides with the row address R_ADD, the row comparison circuit 150 controls the row circuit 120 to activate a redundancy word line instead of the word line designated by the row address R_ADD.
A column fuse circuit 160 stores a column address corresponding to a failed memory cell of the cell array 110 as a repair column address REPAIR_C_ADD. A column comparison circuit 170 compares the repair column address REPAIR_C_ADD stored in the column fuse circuit 160 with the column address C_ADD inputted from the exterior of the memory device. When the repair column address REPAIR_C_ADD coincides with the column address C_ADD, the column comparison circuit 170 controls the column circuit 130 to select a redundancy bit line instead of the bit line designated by the column address C_ADD.
Conventional fuse circuits 140 and 160 usually use laser fuses. A laser fuse stores data of a logic high level or a logic low level according to whether a fuse is cut. Laser fuses may be programmed when they are in the wafer stage. However, once the wafer is mounted on a package, the fuse can no longer be programmed. Moreover, due to its pitch limitations, the laser fuse takes up a significant amount of chip area.
To overcome these drawbacks, U.S. Pat. No. 6,940,751, U.S. Pat. No. 6,777,757, U.S. Pat. No. 6,667,902, U.S. Pat. No. 7,173,851, and U.S. Pat. No. 7,269,047 disclose technology of mounting a non-volatile memory circuit, such as an e-fuse array circuit, a NAND flash memory, a NOR flash memory, an Erasable Programmable Read Only Memory (EPROM), an Electrically Erasable Programmable Read Only Memory (EEPROM), a Ferroelectric Random Access Memory (FRAM), a Magnetoresistive Random Access Memory (MRAM) and so forth, inside of a memory device, and storing repair information in the non-volatile memory circuit.
FIG. 2 is a block view illustrating a non-volatile memory circuit used in a memory device to store repair information.
Referring to FIG. 2, the memory device includes a plurality of memory banks BK0 to BK3, repair information registers 210_0 to 210_3, a configuration information register 210_4, a configuration circuit 220, and a non-volatile memory circuit 201.
The repair information registers 210_0 to 210_3 are provided for the memory banks BK0 to BK3, respectively, and store repair information. The configuration information register 210_4 stores configuration information.
The non-volatile memory circuit 201 substitutes the row fuse circuit 140 and the column fuse circuit 160. The non-volatile memory circuit 201 stores repair information, which includes repair addresses corresponding to all the memory banks BK0 to BK3. Also, the non-volatile memory circuit 201 stores configuration information used for the operation of the memory device. The non-volatile memory circuit 201 may be one among an e-fuse array circuit, a NAND flash memory, a NOR flash memory, an EPROM, an EEPROM, an FRAM, an MRAM and so forth.
Each of the repair information registers 210_0 to 210_3 stores repair information for their corresponding memory banks BK0 to BK3, respectively. The repair information register 210_0 stores repair information of the memory bank BK0, and the repair information register 210_2 stores repair information of the memory bank BK2, and so on. The configuration information register 210_4 stores configuration information to be used in the configuration circuit 220. The configuration circuit 220 may set internal voltage levels and latencies that are to be used for the operation of the memory device based on the configuration information stored in the configuration information register 210_4. The repair information registers 210_0 to 210_3 and the configuration information register 210_4 may store the repair information only while power is supplied. The repair information and the configuration information, to be stored in the repair information registers 210_0 to 210_3 and the configuration information register 210_4, are transmitted from the non-volatile memory circuit 201. The non-volatile memory circuit 201 transmits the repair information and the configuration information when a bootup signal BOOTUP is activated to the repair information registers 210_0 to 210_3 and the configuration information register 210_4.
Since the non-volatile memory circuit 201 is in an array, it takes a predetermined time to read the data stored therein. In short, since the data stored in the non-volatile memory circuit 201 may not be read immediately, it is impossible to perform a repair operation by using the data stored in the non-volatile memory circuit 201 directly. Therefore, the repair information and the configuration information that is stored in the non-volatile memory circuit 201 is transmitted to and stored in the repair information registers 210_0 to 210_3 and the configuration information register 210_4, and the data stored in the repair information registers 210_0 to 210_3 and the configuration information register 210_4 is used for the repair operations of the memory banks BK0 to BK3 and the setup operations of the configuration circuit 220. The process where the repair information and the configuration information, stored in the non-volatile memory circuit 201, is transmitted to the repair information registers 210_0 to 210_3 and the configuration information register 210_4 is called a bootup operation. The memory device may only perform normal operations when the bootup operation is completed, so that the repair information registers 210_0 to 210_3 and the configuration information register 210_4 are setup and are ready to function.
To program the information used for the operation of the memory device (such as repair information and diverse configuration informations) in the non-volatile memory circuit 201, (1) the memory device has to go through a test performed by testing equipment, and (2) the test result has to be transmitted from the memory device to the testing equipment, and (3) the test result has to be analyzed and information generated based on the test result has to be programmed in the non-volatile memory circuit 201. These processes require a significant amount of time, and when tens of thousands of memory devices are tested, analyzing the test results of the tens of thousands of memory devices and programming different information in the tens of thousands of memory devices is complicated and time consuming.